Memory chip

The CAT24C512 is an EEPROM serial 512-Kb I2C internally organized as 65,536 words of 8 bits each. It has a 128-byte page write cache and supports standard (100 kHz), fast (400 kHz), and ultra-fast (1 MHz) I2C protocols. Write operations can be disabled by pulling the WP pin high (this protects the entire memory). External address pins make it possible to place up to eight CAT24C512 devices on the same bus. On-chip ECC (Error Correction Code) makes the device suitable for high-reliability applications.

64-Mbit(8M x 8bit), parallel interface, working voltage: 2.7V to 3.6V

32-Kbit (4K x 8bit), I2C interface, working voltage: 2.5V to 5.5V